One type of memory is a dynamic random access memory (DRAM). DRAMs have several modes designed to reduce current consumption while the memory device is not being accessed. These modes, such as self refresh, active power down, and precharge power down, reduce the current consumed when the memory device is not being accessed. The largest power savings typically can be obtained by ramping down the internal supply voltages and stopping all operations. In this case, data stored in the memory device is lost, but current consumption is reduced to almost zero. This mode is referred to as deep power down (DPD) mode.
Typically, DPD mode in DRAMs is entered using a synchronous DPD command, which may include a burst stop command with the clock enable (CKE) signal logic low. The Joint Electron Device Engineering Counsel (JEDEC), a semiconductor engineering standardization body, has proposed a new feature for low power double data rate (DDR) DRAMs to set a memory device into DPD mode asynchronously. JEDEC has proposed a new, dedicated input pad that when activated sends the memory device into DPD mode. The proposed input pad will be used in stacked die memory applications to allow devices that share pins to be tested or programmed individually. JEDEC proposes that once packaged for normal operation, the input pad will be driven to a logic low to disable the feature and prevent it from being available to the user.
For these and other reasons, there is a need for the present invention.